Journal of Electrical Engineering and Automation

Three-dimensional heterogeneous integrated packaging utilizes silicon through-holes (TSV) technology to achieve efficient chip interconnection, significantly enhancing electronic system performance. However, the significant difference in thermal expansion coefficients between TSV and surrounding materials frequently causes thermal stress issues, severely threatening packaging reliability and device lifespan. This paper thoroughly analyzes the root causes of thermal stress generation in TSV-based three-dimensional heterogeneous integrated packaging. Through theoretical analysis and simulation, it comprehensively explores the distribution patterns of thermal stress. Additionally, multiple innovative thermal stress optimization strategies are proposed, covering material selection, structural design, and thermal management dimensions, with detailed evaluation of their optimization effects. The research findings are significant for promoting the widespread application of three-dimensional heterogeneous integrated packaging technology and improving the reliability and stability of electronic devices.

Silicon through-holes (TSV); Three-dimensional heterogeneous integrated packaging; Thermal stress; Optimization strategies; Reliability